The invention relates to electrostatic discharge (ESD) protection, and more particularly, to ESD protection for circuits operating at high frequencies.
Electrostatic discharge (ESD) is a problem in integrated circuit (IC) technology. An ESD event occurs when a static charge builds up in a human operator or a machine and discharges through an IC during handling of the IC. This discharge typically produces a large current that passes through the IC in a short duration of time, which may result in damage or destruction of the IC if not properly handled or protected.
Several types of ESD circuits have been designed to protect an IC from failure due to an ESD event. Typically, an ESD circuit provides a current path to ground and/or supply when an ESD event occurs so that the high current resulting from the ESD event bypasses the ESD sensitive circuitry in the IC. ESD circuits may be implemented using gate grounded NMOS transistors, diode circuits and zener diodes. Although ESD circuits have proven useful in protecting ICs from ESD events, ESD circuits typically have a capacitive load. As a result, when an ESD circuit is coupled to the output or input of an IC, the capacitive load of the ESD circuit can degrade the performance of the IC at high frequencies.
Therefore, there is a need for an ESD protection scheme that provides increased ESD protection for a circuit operating at high frequencies without degrading the performance of the circuit.